This invention relates to a device for monitoring ATM (asynchronous transfer mode) cells used in an STM (synchronous transfer mode) signal and to a header error check (HEC) device for checking a header error in the ATM cells.
The ATM cells are transmitted in a synchronous transfer mode as the STM signal. The synchronous transfer mode is used on various levels. When transmitted in the synchronous transfer mode of a level M, where M represents a prescribed natural number, the STM signal is called an STM-M signal. An STM-1 signal is transmitted at a bit rate of 155.52 Mbits/s and comprises 2,016 telephone channels. An STM-4 signal is transmitted at a higher bit rate of 622.08 Mbits/s and comprises 8,064 telephone channels. An STM-16 signal is transmitted at a still higher bit rate of 2,488.32 Mbits/s and comprises 32,256 telephone channels.
In the manner which will later be described more in detail, various header error check devices are already known. Such a header error check device has a data input terminal for receiving the STM signal comprising a header part. The header error check device is for checking a header error in the header part. The header part comprises first through P-th header blocks and a header error check block, where P represents a first predetermined natural number. Each of the header blocks comprises first through N-th ATM cell header units, where N represents a second predetermined natural number. The header error check block comprises first through N-th ATM cell header error check units. The first ATM cell header units of the first through the P-th header blocks and the first ATM cell header error check unit constitute a header of a first ATM cell. Likewise, the N-th ATM cell header units of the first through the P-th header blocks and the N-th ATM cell header error check unit constitute a header of an N-th ATM cell. Each of the first through the N-th ATM cell header units and the first through the N-th ATM cell header error check units comprises a third predetermined natural number of bits at a predetermined bit interval.
The header error check device includes a control signal producing section, such as an SDH (synchronous digital hierarchy) terminator or terminating circuit, connected to the data input terminal for producing a collective control signal. In conventional header error check devices, the collective control signal comprises first through N-th control signals. An n-th control signal is for indicating successively the bits of an n-th ATM cell header unit in each of the header blocks and the bits of an n-th header error check unit, where n is variable between 1 and N, both inclusive.
In one of the conventional header check devices, an n-th serial-parallel converter is controlled by the n-th control signal to convert each of the n-th ATM cell header units in first through the P-th header blocks and of the n-th header error check unit to an n-th bit-parallel signal. An n-th cyclic redundancy check circuit carries out cyclic redundancy check on the n-th bit-parallel signal to check the header error in the n-th ATM cell header units of the header blocks.
In another of the conventional header check devices, an n-th cyclic redundancy check circuit is controlled by the n-th control signal to carry out cyclic redundancy check on each n-th ATM cell header unit of the STM signal. The n-th cyclic redundancy check circuit thereby checks the header error in the n-th ATM cell header units of the header blocks.
It is now understood that such a conventional header error check device comprises first through N-th cyclic redundancy check circuits. As a consequence, the conventional header error check devices are bulky and expensive.
Inasmuch as the conventional header error check device can check the header error in the headers of the first through the N-th ATM cells by checking the header error in the header part of the STM signal by the use of the first through the N-th ATM header error check units, it is understood that the header error check device is a device for monitoring the ATM cells. However, the conventional header error check device can not check an information error in an information field of the ATM cell that constitutes the ATM cell together with the header of the ATM cell.